The semiconductor manufacturing industry is known as a complex and demanding business, and it continues to evolve with major changes in device architectures and process technologies. Traditionally, the semiconductor industry has been characterized by sophisticated high-tech equipment, a high degree of factory automation, and ultra-clean manufacturing facilities that cost billions of dollars in capital investment and maintenance expense.
For decades, semiconductor manufacturing was driven by Moore's Law and planar transistor architecture. This provided a predictable, self-sustaining roadmap for transistor cost scaling and well-defined interfaces where each individual process/layer could follow its own technology trajectory independently. However, as the industry scales to provide sub-20 nm nodes and other popular device architectures, such as MEMS, new processes are required, and new approaches for semiconductor manufacturing are being explored and implemented.
For sub-20 nm nodes, entirely new device architectures are needed. In parallel, the rapid growth in the Internet of Things (IoT) is driving the MEMS market. These changes have presented difficult and unprecedented challenges for the industry, generally resulting in lower manufacturing yields.
In order to achieve acceptable yield and device performance levels with these new architectures, very tight process specifications must be achieved. Thus, better process control and integration schemes are needed now more than ever.
One example of a specific current challenge for the industry is lithography processes for sub-20 nm node manufacturing. EUV lithography techniques are known but have not yet been widely adopted for production, and therefore, 193 nm immersion lithography must extend its capability via multi-patterning schemes, which adds masks and process steps, and is therefore complicated and expensive.
Various processes also require more complex integration, and therefore can no longer be developed independently of each other. For example, the three-dimensional architecture of finFET's and 3-D NAND's, as well as the complex relationships between corresponding process steps, have changed the way that process variabilities can affect device performance and yield. As an example, many semiconductor manufacturers are experiencing lower yield on their finFET lines, and the need to increase yield is urgent. In the memory space, 3-D NAND has become the dominant architecture, and process control is a key issue for 3-D NAND process layers. The IoT space is increasingly dominated by the “More-than-Moore” trend, where devices incorporate technologies that do not necessarily scale to Moore's Law. This growing market space is driven by diversified and specific processes, and the need for new ways to improve yield and reduce manufacturing costs when implementing manufacturing solutions is needed.